It is often desirable to use memory devices that will retain information even when power is temporarily interrupted, or when the device is left without applied power for indefinite periods of time. Semiconductor memories with this characteristic are known as nonvolatile memories. One variety of nonvolatile memory with broad application is the electrically erasable and programmable read only memory (“EEPROM”). Information can be electronically stored and erased in memory cells of EEPROM.
A conventional EEPROM device has an array of memory cells arranged in an N×M matrix on a single chip where N is the number of rows and M is the number of columns. The array is divided into a number of sectors, each of which can be separately selected for erasure. Each sector is formed of a predetermined number of rows which are grouped together. The 16 Mb (megabit) flash memory shown in FIG. 1 is divided into 32 sectors. Each sector has a size of 64 k bytes and may include 256 rows and 256 columns.
Each cell has an N-type source region and an N-type drain region integrally formed within a P-type substrate. A floating gate is separated from the substrate by a thin dielectric layer. A second dielectric layer separates a control gate from the floating gate. A P-type channel region in the substrate separates the source and drain regions. The control gates of the cell transistors are coupled to word lines, and the drains thereof are coupled to bit lines. In the illustrated EEPROM where memory cells are divided into a plurality of sectors, the source region of each cell transistor is connected to a common node within each sector. This node is called Vsc. Thus, all of the memory cells within the sector are erased simultaneously and erasure is performed only on a sector-by-sector basis.
EEPROMs typically are programmed by injecting hot-electrons to the floating gate when a high voltage is applied to the control gate and the drain region while low voltage is applied to the source region. For example, the drain voltage may be set to approximately +4.5 volts and the control gate voltage may be set to approximately +9 volts while the source region is held at a ground potential. In an erasing operation, flash memory cells in a sector may be simultaneously erased by means of the so-called Fowler-Nordheim (F-N) tunneling mechanism. A positive voltage (e.g., +6 volts) is applied to the source region, a negative voltage (e.g., −9 volts) is applied to the control gate, and the drain region is allowed to float. A strong electric field between 12 to 9 MV/cm is generated between the control gate and the substrate under this bias condition, so that negative charges accumulated in the floating gate are discharged into the source region through the thin insulator. In a read operation, the source region typically is held at a ground potential (0 volts) and the control gate has a voltage at about +5 volts. The drain region is connected to a voltage between +1 to +2 volts. The above examples are given for explanation only and other voltage values may be used so as to provide similar programming, erasing, and reading operations.
A conventional erase method sequentially erases every memory cell in sectors to be erased. If a cell fails verification, an erase pulse is applied to all sectors to be erased and the cell is verified again. This process repeats until the cell passes the verification and then the next cell is verified. If a cell is very hard to be erased, applying erase pulses repeatedly may over erase normal memory cells.
To avoid over-erase, an improved erase method as shown in FIG. 2 uses sector erase flags for each sectors. Once all memory cells in a sector are successfully erased and verified, the erase flag of that sector is set and that sector is not erased again. Accordingly, normal sectors are not over erased due to the presence of a hard-to-erase memory cell in another sector. However, because of the repeated erasure attempts, a hard-to-erase memory cell still consumes excessive time for verification. Over-erase is still possible under the improved technique. For example, if a cell takes 100 erase pulses to pass verification, it requires about 21 seconds, assuming each verification time period is about 200 ns and each erase pulse time period is about 10 ms.
To reduce the total erase time, another improved method as shown in FIG. 3 has an address register for each sector to record an address of a cell that fails verification in the sector. For each sector, memory cells are sequentially verified. If a cell fails verification, the address is stored in the sector address register. Thus, after applying an erase pulse, there is no need to begin verification from the first memory cell in the sector. Instead, verification continues on the memory cell that previously failed the verification. However, sector address registers takes chip space from memory cells. For example, in a 16M flash memory with 35 sectors, the area occupied by the sector address registers is about 0.89 mm2 out of the 14 mm2, the 16M chip size.